Develops a low-power multiphase clock generator, employ static demultiplexers and proposes a hybrid design to reduce the power. The power model is based on the weighted transition count (WTC). The internal gates of a latch consume 2 transitions per cycle when the data changes. The clock and data input capacitances of a latch are assumed the same as that of a regular gate. A double-latch FF thus consumes 5 transitions including the interconnection between latches when the data changes.