The main task of the fault simulation process is to manage the propagation of the fault effects through the circuit. This paper addresses the problem of propagating gate delay faults in synchronous sequential circuits. The rules for propagating such gate delay faults without any restriction on their size and without considering explicitly the fault size, will be established in this paper. These propagation rules are the foundations of the fault simulator we are developing. This fault simulator will be suitable for simulating gate delay fault in synchronous sequential circuits whatever the fault size may be. >