In this paper, we present an efficient hardware implementation of a Context Adaptive Variable Length Coding (CAVLC) module for an H.264/AVC video encoder. To improve timing performance, a three-stage pipeline architecture is proposed including: input data statistical analysis, encoding and packing. The context information and coding tables are stored in memory elements. To minimize the hardware implementation overhead and increase the system performance, in some sub-encoders, the codewords are calculated on-the-fly instead of being stored in look-up tables. The proposed architecture has finally been implemented using a low power CMOS 65nm technology from STMicroelectronics. The design is able to operate up to 715MHz. At 550MHz, the design complexity is 33Kgates for a power consumption of 20mW. The design is initially targeted to CIF video format; however, it is obviously suitable for real-time HD 1080p video format.