Timing measurements of synchronization circuits

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 08 Oct 2003Publisher:IEEE Comput. SocJournal:Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings.

Authors: Yaron Semiat; Ran Ginosar;

doi: 10.1109/async.2003.1199167

Timing measurements of synchronization circuits

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Abstract

A regular (two-flop) synchronizer and six multi-synchronous synchronizers are implemented on a programmable logic device and are measured. An experimental system and method for measuring synchronizers and metastable flip-flops are described. Two separate settling time constants are shown for a metastable flop, confirming earlier results of Dike and Burton [1999]. Clocking cross-talk between asynchronous clocks is demonstrated. The regular synchronizer is useful for communications between asynchronous clock domains, while the other synchronizers can provide higher bandwidth communications between multi-synchronous and mesochronous domains.

Related Organizations

Technion – Israel Institute of Technology
Israel

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