In this work, the design of a dual loop flipped voltage follower (FVF) based low-dropout regulator (LDO) to achieve fast transient response is proposed for all-digital phase locked loop (ADPLL) in the RFID application. With the help of an additional reference generation loop in FVF LDO and the cascaded structure, high power supply rejection ratio (PSRR) is achievable. This design is fabricated in GF 40nm CMOS technology. The FVF LDO core only occupies small area of 0.036 mm2. This area also includes 80pF on chip capacitor. Without large off-chip capacitor, this LDO is suitable for system-on-chip (SoC) requirement. Post layout simulation shows that fast response of 45ns and high PSRR of −42dB through up to 10GHz frequency range.