Power-gating (PG) architectures employing nonvolatile state/data retention are expected to be a highly efficient energy reduction technique for advanced CMOS logic systems. Recently, two types of PG architectures using nonvolatile retention have been proposed: One architecture is our proposed nonvolatile PG (NVPG) using nonvolatile bistable circuits such as nonvolatile SRAM (NV-SRAM) and nonvolatile flip-flop (NV-FF), in which nonvolatile retention is not utilized during the normal SRAM/FF operation mode and it is used only when there exist an energetically meaningful shutdown periods given by break-even time (BET). In contrast, the other architecture employs nonvolatile retention during the normal SRAM/FF operation mode. In this architecture, an even short standby period can be replaced by a shutdown period, and thus this type of architecture is also called normally-off (NOF) rather than PG. In this paper, these two PG architectures employing spintronics-based nonvolatile retention are systematically analyzed using HSPICE with a highly accurate magnetoresistive-device macromodel. The NVPG architecture shows effective reduction of energy dissipation without performance degradation, while the NOF architecture has no energy reduction effect and causes severe performance degradation.