An energy-efficient successive approximation register analog to digital converter in 180nm

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 01 Dec 2010Publisher:IEEEJournal:2010 IEEE Asia Pacific Conference on Circuits and Systems

Authors: Taimur Gibran R. Kuntz; Saeid Nooshabadi;

doi: 10.1109/apccas.2010.5774967

An energy-efficient successive approximation register analog to digital converter in 180nm

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Abstract

This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations. This FOM is close to reference designs reported in 90nm.

Related Organizations

Michigan Technological University
United States
Universidade Federal de Santa Maria
Brazil

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