This paper describes a new architecture for high-resolution digital PWM (DPWM) generator used in digitally-controlled DC-DC converters, PWM time resolution is determined by the difference between two (or more) gate delays, while that of conventional DPWM circuits is determined by gate delay itself. The proposed DPWM circuit can achieve fine time resolution with small circuits, and has low power consumption. We have also developed a systematic design method for this DPWM circuit based on the extended Euclidean algorithm. A design example that achieves 10 ps time resolution for 80 ns cycle time (i.e. 13-bit resolution) is shown to demonstrate the effectiveness of the proposed DPWM architecture.