With the reduction in supply voltages in order to minimize power dissipation, arises the need for a low voltage analogue multiplier. Developed is a multiplier that operates at as low a voltage as that required to bias a single n-MOS transistor by utilizing CMOS, as against the conventional multipliers which use either n-MOS or p-MOS transistor in the core. Moreover, in contrast to the open loop implementations of the prevalent multipliers, the proposed multiplier incorporates a negative feedback loop within the core circuitry, the main import being that the poles of the system can be made a complex conjugate pair located anywhere in the left half of the s plane, making the multiplier suitable for wide-band or high speed applications in the field of communications. The canonic structure of the proposed multiplier further enhances the speed of the circuit.