Area efficient current steering DAC using current tuning

descriptionPublicationkeyboard_double_arrow_right Article , Conference object 26 Jun 2003Publisher:IEEEJournal:Asia-Pacific Conference on Circuits and Systems, volume 1, pages 559-564

Authors: Sunil Rafeeque;

doi: 10.1109/apccas.2002.1115066

Area efficient current steering DAC using current tuning

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Abstract

A 10 bit segmented (5+5 bit) high speed current steering DAC is presented in this paper. Devices with small area are used to reduce the total area without affecting linearity. A current tuning loop is suggested to overcome the sizing mismatch error. The master slave concept is used along with this to generate multiple copies of weighted current sources. Sizing reduces the area requirement to 20% of the 2/sup n/ unit cell design. The tuning reduces the DNL and INL to 0.1 LSB without considering any random error.

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Indian Institute of Technology Madras
India

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