This paper describes a design procedure for a CMOS voltage doubler. Test-bench circuit are used to verify the performance of the design. Several equations that relate performance parameters with design variables are presented. This set of equations considers both transient and steady state behavior. Various known energy losses such as switching and conduction losses were taken into account for transistors sizing. The effects of the characteristics of the pump capacitors are analyzed and evaluated through electrical simulations. A design example based on AMS 0.35μm process is presented.