A large and growing fraction of the power in modern VSLI chips is dissipated by the drivers of external bus lines. A novel bus system drastically reduces power and noise by using a central driver chip which periodically attempts to charge and to discharge the bus lines. The transmitters of the selected chip inhibit the charge process for the establishment of a 'low' signal. The central driver latches the signal state after the inhibit phase. The authors explain the inhibit driver principle in comparison with the usual push-pull system, present the timing characteristics, and report on the design and the measured results of an experimental central driver chip in full-custom CMOS. >