This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B/sup 2/CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B/sup 2/CMOS to CMOS, BiNMOS, and BS-BiCMOS for sub-0.5 /spl mu/m BiCiMOS technologies. Simulation results have shown that the B/sup 2/CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B/sup 2/CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B/sup 2/CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V. >