A single-chip decoder for the POCSAG radiopaging code

descriptionPublicationkeyboard_double_arrow_right Article 01 Jan 1990Publisher:Institute of Electrical and Electronics Engineers (IEEE)Journal:IEEE Transactions on Consumer Electronics, volume 36, pages 897-902 (issn: 0098-3063,

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Authors: S. Drude;

doi: 10.1109/30.61571

A single-chip decoder for the POCSAG radiopaging code

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Abstract

An integrated low power consumption POCSAG (Post Office Code Standardization Advisory Group) decoder and pager controller circuit is described, and some information on the SAC-MOS (self-aligned contact CMOS) process used to manufacture it is given. The decoder implements digital filtering, clock recovery, synchronization, error detection and correction, and user interface functions. Since this IC has nonvolatile user address memory (EEPROM) on chip, only two integrated circuits are required to build a complete miniature alert-only pager. The characteristics of the decoder are summarized, and application examples are shown. >

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