A principal limitation in accuracy for scientific computation performed with floating-point arithmetic may be traced to the computation of repeated sums, such as those which arise in inner products. \textit{U. W. Kulisch} and \textit{W. L. Miranker} [Computer arithmetic in theory and practice (1981; Zbl 0487.65026)] have shown one way out of this limitation to accuracy by including a fifth floating-point operation, called the inner product, to the conventional four floating-point operations. The authors propose the design of a systolic super summer, a cellular piece of hardware for the high throughput performance of repeated sums of floating-point numbers. The floating point summands are converted into a fixed point form by a sieve-like pipelined cellular packet-switching device with signal combining. The emerging fixed-point numbers are then summed in a corresponding network of extremely long accumulators (i.e., super accumulators). At the cell level, the design uses a synchronous model of VLSI; at the architectural level, the design is asynchronous. The throughput per unit area of hardware approaches that of a tree network, but without the long wire and signal propagation delay that are intrinsic to tree networks.