To enable circuit design using tunnel field-effect transistors (TFETs), a physics-based model based on nonlocal band-to-band tunneling is developed. To maintain accuracy, the tunneling lengths are estimated assuming that both vertical and horizontal tunneling paths exist in the device. The static current-voltage characteristics are modeled, including the diode currents and Esaki tunneling. Parasitic capacitances and resistances are included to enable transient circuit analyses. The model is validated by comparison with measurements of silicon TFETs, as well as with semiconductor device simulations based on nonlocal band-to-band tunneling. The model accounts for TFET behavior in circuits, as demonstrated by simulations of inverters and static random access memories. Consequently, the model can be used to develop TFET circuits for low-power applications.