We report the first observation of voltage gain in the capacitively coupled single-electron transistor (SET). Using parallel-plate and interdigital geometries for the gate capacitor (Cg=1.2 and 0.4 fF) and ultrasmall tunnel junctions with capacitances near 0.2 fF, we find maximum voltage gains of 2.8 and 1.5, respectively. The leakage resistance of the gate is of the order 1012 Ω for the parallel-plate capacitor and greater than 1018 Ω for the interdigital capacitor.