To realize ULP fractional-N ADPLL with low jitter and low spurs, the first-order DSM-based fractional controller works in conjunction with a highly linear DTC. The rms jitter can be improved when compared to using higher-order DSM, and for this a DTC with high linearity is required. To realize a linear and high-energy efficient DTC, an isolated constant-slope method is proposed. Thanks to the isolated operation of DTC, the proposed DTC can potentially work at a high sampling frequency with small power consumption while maintaining good linearity with high energy efficiency. Furthermore, the auto-zero offset switch mitigates part of the supply noise, which can improve the linearity in SoC environment. The proposed fractional-N ADPLL achieves good fractional spurs while maintaining a low jitter performance and low power, which proves the linearity and power efficiency of the DTC. The gain calibration of TA demonstrates a steady in-band phase noise of the ADPLL over the temperature variations. The measurement of lock time proves the effectiveness of the always-on coarse PLL in the feedback loop.