An ultra-compact three-stage amplifier is proposed by merging current buffer Miller compensation with parallel compensation, which achieves significant improvement in area efficiency without sacrificing the gain-bandwidth product (GBW) and power. Fabricated in 0.35 m CMOS the amplifier measures 4.98 MHz GBW at 150 pF load while drawing 20 A at 2 V. The entailed compensation capacitance is minimised to 1.5 pF and the chip size is merely 0.012 mm 2 .