Abstract A 4 K-bit SRAM with 0.2 um Double Fully-Depleted Silicon-On-Insulator (DSOI) CMOS process is designed to examine circuit total ionizing dose (TID) and the back gate bias effect. Preview researches show that MOSFET electrical parameter shift due to TID damage can be compensated by back gate bias of the FDSOI technology. We can control the NMOS/PMOS back gate separately and discretionarily with DSOI structure which could improve circuit radiation tolerance. TID experiment results show that the total ionizing dose capability of the 4 Kb SRAM test chip is above 1 M rad (Si).