Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

descriptionPublicationkeyboard_double_arrow_right Article 01 Aug 2008 English Publisher:Elsevier BVJournal:Microelectronics Reliability, volume 48, pages 1,300-1,305 (issn: 0026-2714,

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Authors: Peter Moens; Geert Van den Bosch;

doi: 10.1016/j.microrel.2008.06.048

Reliability assessment of integrated power transistors: Lateral DMOS versus vertical DMOS

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Abstract

The total safe operating area of both lateral and vertical integrated DMOS power transistors is evaluated. The electrical, hot carrier and thermal safe operating area of both devices types is investigated, and a comparison is made. It is found that the vertical DMOS exhibits a superior hot carrier and electrical safe operating area, mainly being due to the absence of a field oxide dot in the device drift region. The thermal safe operating area of LDMOS and VDMOS is identical.

Related Organizations

Katholieke Universiteit Leuven
Belgium
ON Semiconductor (United States)
United States

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