Poly resistors around the device can be used to perform fast in situ heating on a single device on wafer level. This is a commonly used technique to apply time-saving NBTI stress in the production line [Muth W, Walter W. Bias temperature instability assessment of n- and p-channel MOS transistors using a polysilicon resistive heated scribe lane test structure. Microelectron Reliab 2004;44(8):1251– 62; Schluender C, Vollertsen RP, Gustin W, Reisinger H. A reliable and accurate approach to assess NBTI behavior of state-of-the-art pMOSFETs with fast-WLR. In: 37th European solid state device research conference ESSDERC; 2007. p. 131–4; Ting-Kang, Chi-Shiun Wang, Kuan-Cheng Su. Self-heating p-channel metal-oxide-semiconductor field-effect-transistors for reliability monitoring of negativebias temperature instability. Jpn J Appl Phys 2007;46(12):7639–42]. We demonstrate how such a structure can not only be used as a heating element but also as a fast tool for switching the temperature. The cool down process as well as the heating procedure are rigorously analyzed and found to be very fast (<1 s) and independent of the difference between actual and target temperature. Thus, we are able perform NBTI at a certain stress temperature, which generates a certain degradation level, while the recovery itself can be studied at arbitrary temperatures. By using this technique, our understanding of the recovery physics can be probed in an unprecedented manner. In order to guarantee that our measurements probe the ‘classic’ NBTI mechanisms, unpolluted by tunneling currents in thin oxides and the strongly process dependent impact of nitridation, we use PMOS transistors with 30 nm SiO 2 gate oxides.