A large variety of tasks in the fields of image processing and numerical computation demand a very high instruction throughput. The figure of 109 instructions/sec has for instance been cited as representing typical computational load for tasks in low-level image processing). Such a high instruct ion rate cannot be supported by conventional serial (Von Neumann) computer architecture. A close analysis of many image processing algorithms reveals that the same sequence of instructions are normally repeated on every pixel item, pixel by pixel, over the entire image. This inherent parallelism can be exploited to achieve very high computational throughputs. We have been investigating a number of non-Von Neumann architectures which seem to offer a suitable solution (2. One such architecture — the Single Instruction Multiple Data stream (SIMD) type has shown great promise in the past 3,4,5, but has needed the emergence of VLSI for it to be truly feasible as a cheap and compact system. Such a VLSI system under implementation is the GEC Rectangular Image and Data (GRID) processor system 6). An alternative approach relies on the identification of common operators, which make up more complex algorithms, and their customizing as special-purpose integrated circuits that operate on an incoming stream of video data.