Some of the current microprocessors provide a prefetch instruction, but either the instruction is treated as a NOP, (e.g. Digital Alpha EV4/5), or only a small number of outstanding prefetches is permitted (e.g. MIPS R10K). This paper discusses the design and implementation of the hardware support required to fully support the prefetch instruction for the Digital Alpha architecture. The prefetch support is implemented in a cycle-level functional simulator of the Alpha architecture.