In this chapter architectural aspects of time-to-digital converters are discussed in detail. The design challenges are a high dynamic range, small offset and gain error, high linearity, a small die area, and finally a low power consumption. The time resolution is independently addressed in Chapter 5. Several architectures are proposed that particularly focus on at least one of the design challenges. A bipolar TDC allows for signed measurement without offset error. A loop architecture enables long measurement times with reasonable area consumption. A linear loop extension improves the linearity impairments of the basic loop architecture. For long measurement times a hierarchical TDC system can further reduce the power consumption. For complex measurement tasks that would require multiple time-todigital converters a multi-event TDC can be used to reduce the number of converters and to improve matching. An on-chip measurement and characterization engine allows for low cost TDC characterization. Finally, a time domain quantizer is discussed that maps a discrete valued continuous time signal to a discrete time raster.