Cryptographic hash functions are used for digital signatures; message authentication codes (MACs) and other forms of authentication. National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. Hardware performance evaluation of the candidates of this competition is a vital part of this contest. In this work we present an efficient FPGA implementation of Grostl, one of the final round candidates of SHA-3. We show our results in the form of chip area consumption, throughput and throughput per area. We compare and contrast these results with other reported implementations of Grostl. Our design ranks highest in terms of throughput per area, achieving figures of 5.47 Mbps/slice on Virtex 7 and 5.12 Mbps/slice for Grostl-256 on Virtex 6.