In this paper, a systolic inversion architecture is proposed based on an optimized version of the Modified Extended Euclidean Algorithm (OMEEA). The proposed OMEEA employs signal reusability and simplification of the algorithmic control logic to achieve a less complex, hardware oriented version of Modified Extended Euclidean Algorithm. The resulting proposed systolic inversion architecture highlights the benefits of OMEEA and achieves very interesting results in terms of latency, critical path delay and gate-MUX-Flip Flop number.