This paper teaches the way to reduce parasitic couplings by using special device architecture together with optimized routing. Two main options are proposed in order to tackle parasitic coupling related issues: a low stray field monolithic inductor implementation and conformal Faraday cage shielding used for on chip interconnect lines. Both examples have been implemented on silicon and on-wafer two ports S-parameters measurements have been carried-out against frequency up to 50 GHz. It is shown that these structures can decrease parasitic coupling from 20 to 30 dB without any impact on application footprint. In case of interconnect lines, the proposed approach also allows saving area and optimizing routing. A compact modeling is proposed for the device inductor while a BBS (Broad Band Spice) extraction is performed for the micro coaxial lines. Both modeling approach are corroborated to measurements. Based on the available data, correlation is found satisfactory between measurements and electrical modeling. On the other side, we show experimentally that both proposed approaches allow reducing inductive crosstalk by at least 100 times or 20 dB