Network-on-Chip (NOC) has developed as a new method to integrate large number of cores on a single silicon die. Processing elements are interconnected through packet-based network in NOC architecture. The NOC architecture consists of physical layer, the data link layer and the network layer of OSI protocol stack. In this paper, NOC router based packet switching network with Round Robin Arbiter has been proposed. In packet switching method, Data's are transmitted in short packets. Packets are received, stored briefly and forward to the next node. All packets are routed through the shortest paths and maintaining the performance of Noc in the presence of faults. The packet switching network with virtual channel flow control provides the flexibility, area and energy efficiency. NOC provides essential advantages such as scalability, increased parallelism of partial dynamic configuration. The main focus of this work is to reduce the frequent checking of unconnected nodes and making the return path delay. Finally, the packet switched NOC using Round Robin arbiter is incorporated into AES Encryption and Decryption algorithm, which is used to protect the information. In this proposed design, is to reduce the power, delay and area and also improves the performance of the architecture. NoC data transport medium, which is commonly occupied by FIFO buffers and routing logic. The proposed packet switched network on chip using round robin algorithm based AES encryption and decryption has been simulated by using Model Sim 6.3c and synthesized by Xilinx 12.4I design tool.