Efficient processor arrays for the implementationof the generalised predictive-control algorithm
Copyright policy )Efficient processor arrays for the implementationof the generalised predictive-control algorithm
Four processor array architectures for the implementation of the generalized predictive control (GPC) algorithm are introduced. The first is derived by interconnecting the arrays required for the execution of GPC partial algorithms, while the remaining three are found by mapping the separate arrays sequentially onto one. The exposed architectures allow a remarkable reduction in the execution time of a complete cycle of the GPC algorithm, compared with the solution on a single general-purpose processor. It is also emphasized that the GPC partial algorithms and the corresponding array architectures form the basis of unified hardware environment for fast execution of most existing control laws.
- New York University United States
- University of Patras Greece
generalized predictive control algorithm, Design techniques (robust design, computer-aided design, etc.), Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), parallel algorithms, processor array architectures, Control/observation systems involving computers (process control, etc.)
generalized predictive control algorithm, Design techniques (robust design, computer-aided design, etc.), Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.), parallel algorithms, processor array architectures, Control/observation systems involving computers (process control, etc.)
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