Smart vision systems on a chip are promising for embedded applications. Currently, flexibility in the choice of integrated pre-processing tools is obtained at the expense of total silicon area and fill factor, which are otherwise optimized provided that the sensor performs a specific task. We propose a new architecture based on macropixel-level processing to improve the trade-off by using the same processing elements (PEs) for a whole group of pixels. In this paper, we show through functional simulations the feasibility of using macropixel PEs, with analog operative parts to avoid analog to digital converter (ADC) bottlenecks and digital controls, distributed in and out of the matrix of pixels. PEs are designed to be suitable for coefficient-reconfigurable spatial filtering as well as temporal difference. Sharing electronics among several pixels and matching existing algorithms to the target architecture allow for such programmability without degrading pixel area nor fill factor. Keywords— Smart image sensor, vision system on a chip (VSoC), focal-plane array, algorithm-architecture matching, mixed analog-digital electronics.