Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval
Copyright policy )Combining flash memory and FPGAs to efficiently implement a massively parallel algorithm for content-based image retrieval
With ever larger and more affordable storage capabilities, individuals and companies can now collect huge amounts of multimedia data, especially images. Searching such databases is still an open problem, known as content-based image retrieval (CBIR). In this paper, we present a hardware architecture based on FPGAs which aims at speeding-up visual CBIR. Our architecture is based on the unique combination of reconfigurable resources and flash memory, allows for a speed-up factor of 45 as compared to existing software solutions.
high performance computing, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], reconfigurable architecture, image processing
high performance computing, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], reconfigurable architecture, image processing
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