A comparative study of Hierarchical Enumerative Coding (HENUC) for FPGA and DSP implementation is presented. HENUC is a lossless fixed-point entropy coding algorithm employed by a wavelet-based image encoder, which provides good compression performance for the locally stationary image data. It has been implemented in our previous work on an Altera's 40nm Stratix IV EP4SGX230 FPGA as a hardware IP accelerator in a Nios II based system. In this paper, we implemented it on a Texas Instruments's (TI) 40nm Integra C6A816x/AM389x DSP. We present experimental results regarding the execution time, resource utilization and core power consumption of the two implementations and we evaluate their throughput and power efficiency. Our results show that a highly parallelized FPGA implementation at 100MHz is 12.3× faster than a highly tuned DSP implementation running at 1.5 GHz and consumes 2.4× less power, they also show that the proposed algorithm is more suitable for hardware implementation.