The need for small chip covered area in most handheld devices with out sacrifices in computational power introduces an interesting problem concerning expensive, computational intensive operations, like GF(2 k ) inversion which is widely used in cryptography. This paper addresses this problem by proposing a systolic inversion architecture for GF(2 k ) fields. This architecture is based on an extended analysis on an optimized version of Modified Extended Euclidean Algorithm (OMEEA) that is using signal reusability and simplification of the control signals with regard to hardware design and manages to make the inversion process less complex. The proposed one dimensional systolic inversion architecture based on OMEEA was measured in terms of hardware components number, latency and critical path delay with very interesting results when compared to other well known designs thus proving the efficiency of the analysis on OMEEA algorithm.