Research interest in finite control set model predictive control (FCS-MPC) for power conversion devices is growing in recent years. Particularly, long prediction horizon FCS-MPC provides promising results in recent research works. However, its practical implementation is not generally straightforward due to its inherently large computational burden. To overcome this obstacle, the problem can be formulated as a least-squares integer program. Sphere decoding algorithm (SDA) is a branch and bound algorithm proposed in previous works as an efficient approach to solve this problem. In these works, SDA is formulated as an iterative process where simultaneous search is not possible. A parallel and fully scalable SDA design is proposed in this paper. The design is implemented in the FPGA of a modern Field Programmable System on Chip (FPSoC) platform. Thanks to the proposed parallelization, the required execution time is greatly reduced. Experimental results prove the feasibility and performance improvements of the proposed implementation.

ECPE Joint Research Programme 2020/PC04

Ministerio de Universidades FPU18/02704