Building on TalTech’s expertise in the field of computer engineering and its high-level capacity in the domain of diagnostics and testing of nanoelectronic systems, this project aims at establishing in TalTech, with the strong support of the Advanced Partners, the capacity to R&D&I a complete customised AI-chip design flow. The research ambition of the TAICHIP (TalTech AI-chip) action is a leading-edge forward-thinking R&D framework for reliable and resource-efficient custom AI-chips based on open HW architectures (e.g., RISC-V, NVDLA), open EDA (Electronic Design Automation) tools, methodologies and implementation technologies satisfying the requirements of AI applications of tomorrow. TAICHIP project also allows building at TalTech the necessary scientific knowledge, research skills, administrative and management skills, as well as strengthening its advanced training and education capacity. Evenly related to the central goal are the additional measures that focus on building the supporting capacities, as well as dissemination, exploitation and communication, and public policy focused activities.

Reliable electronic systems are crucial in a wide range of applications, such as space missions, avionics, automotive, smart industry, medicine, banking, nuclear power plants, high energy physics research. With the introduction of advanced semiconductor technologies, the design of reliable electronic systems has become more challenging, requiring novel analysis and design methods and tools. The ultimate goal of TWIN-RELECT project is to boost the scientific and innovation capacity of UTH in the design of reliable electronic systems through strategic networking with three advanced partners: IHP - Institute for High Performance Microelectronics from Germany, National Center for Scientific Research (CNRS) from France, and University of Manchester from United Kingdom. The TWIN-RELECT collaboration will employ a set of actions grouped into five main components: (i) joint exploratory research aimed at the development of a novel tool for simulation of reliability effects and design of reliable integrated circuits, (ii) knowledge transfer through staff exchanges, joint training experiments, supervision of early stage researchers and organization of training schools, (iii) knowledge transfer in relation to research management and administration, (iv) enhancement of networking capacity through organization or workshops, business events, special sessions at conferences, webinars with related projects and international symposium, and (v) establishment of conditions for long term collaboration between UTH and advanced partners, as well as interested stakeholders.

Voltage droops are unpredicted drops in the supply voltage of computer chips, which often occur as a result of nearby bursts of high intensity circuit activity. This proposal is concerned with fast voltage droops, where voltage drops within a few clock cycles. This means that any dynamic response must take place within one or at most two clock cycles. A promising direction for combining the advantages of a stable reference clock with a small response time are mixed-signal control loops, in which voltage measurements are digitized and control decisions are taken by digital logic. However, digitally measuring a dynamically changing voltage may cause metastability of the sampling circuit. Conventional approaches employ synchronizers to make the probability of metastable upsets negligible, which costs 2-3 clock cycles of additional delay. Based on results of the ERC starting grant project "A Theory of Reliable Hardware,'' we provide a simple, compact circuit that guarantees the desired behavior without incurring synchronizer delay. This yields a practical method for adaptive response to fast droops, which bears the promise of increasing computational efficiency. Conservative estimates suggest performance improvements of at least 5%, which would be of substantial economical interest. The main obstacle to commercialization is a gap between theory and practice: Without an existing implementation, it takes a long time to develop a product and the associated risks are high. In this project, we will overcome this hurdle by developing, producing, and evaluating an Application-Specific Integrated Circuit (ASIC) demonstrator for our approach. We complement this primary goal by tasks aiming at maximizing impact: publication of results in high-profile scientific venues, patent protection to facilitate commercialization, and outreach to potential industry partners for developing products.

The project aims to realize a strong methodology for the development and design of a radiation hard non-volatile memory technology by using standard CMOS silicon processing. Since standard silicon memories, such as flash memories tend to fail under irradiation, a new approach is envisaged: the development of a specific memory technology, so called resistive random-access memory (RRAM), which is able to sustain heavy ions and other charged particles. The switching effect of RRAM devices is caused by chemical Redox-reactions, therefore, radiation effects like total ionizing dose and single event effects don’t affect the switching mechanism. Semiconductor memories, among rad hard integrated circuit scenario, are one of the most critical topics for space applications. Actually both volatile and nonvolatile memories, excluding few exceptions, are integrated using standard processes and standard architectures. This means that the final device is typically at least Rad tolerant and not Rad Hard and failure during mission is avoided using Error Correcting Code techniques including redundancy at the board level. The basic goal of the project is to give a methodology for the development of a new rad-hard nonvolatile RRAM memory with high-performance features like good retention, re-programmability and cycling, and realize a prototype (1Mbit RRAM memory) in order to validate the approach.