Efficient multiplication is crucial in digital signal processing and arithmetic computing systems, particularly on low-power, portable embedded platforms. The Modified Booth algorithm effectively reduces the number of partial products and improves performance in multiplication operations. This work presents the design and simulation of a low-power VLSI multiplier using a modified Booth encoding scheme, optimized for reduced switching activity and minimized hardware complexity. The proposed architecture is implemented in Verilog HDL and evaluated for power, delay, and area using industry-standard EDA tools. Simulation results demonstrate significant power savings and reduced critical path delay compared to conventional multipliers, making the design well-suited for high-performance and energy-efficient digital systems.