Processing of a digital image by the use of computer algorithm is usually referred as digital image processing. However, some unwanted signals capture the image which is termed as noise. Thus the digital image filtering technique is frequently used to eliminate noise. Generally image filters are following up software approach in systems. But hardware implementation prefers in comparison with software implementation for better processing speed. With a boost in the VLSI technology hardware implementation has given a better choice. In the present paper, a hardware implementation method of a Switching non linear Image Filter is proposed with 3X3 window size. Virtex-7 VC707 was used for design, simulation and synthesis process. The performance analysis of the switching median filter was evaluated for different image set (Lena, Cameraman, and Barbara). The max operating frequency attained was 397 MHz. The minimum delay achieved was approximately 2.41ns. The Verilog language was utilized to aim two-dimension switching image filter using ISE (Xilinx) tool. The proposed algorithm for the Switching Image Filter is working on sorting and finding the median values. The comparison has been done with peak signal to noise ration, processing time and the visual inspection observed on each filter.