Nanoelectronics relies on multiple semiconductor processes resulting in pattering of macroscopic objects (silicon wafers) at nanoscale level. The International Technology Roadmap for Semiconductors of semiconductor industry pursues increasing resolution of lithographic features and density of the circuit elements. The rapid pace of progress in the semiconductor manufacturing dictated by the Moore’s economic law also introduces a variety of novel nano-structured materials having poorly understood hazardous properties. In order the address this concern the NanoStreeM project partners have assembled lists of nanomaterials, which are (i) currently used by the semiconductor manufacturers or that are suspected to be produced in different processing steps (ii). In order to facilitate risk assessment, we have looked into a number of parameters, which are requested by the ISO Technical Standard 12901 “Occupational risk management applied to engineered nanomaterials -- Parts 1 and 2”. Eight partners submitted information on nanomaterials used or generated within their facilities: CEA, L Foundry, NXP IMEC, Intel, Soitec, STMicroelectronics and Texas Instruments. A total of 47 examples of purchased nanomaterials were submitted and 16 scenarios were identified and submitted where there was a suspicion that nanomaterials may be generated. In terms of the purchased nanomaterials, nearly all materials submitted fell into the category of slurries used for Chemical Mechanical Polish with the exception of one other nanomaterial, a coloured photoresist, used in the photolithography process. The partners submitted also 16 different scenarios for which nanomaterial generation is suspected. These included opening of process chambers or exhaust lines of manufacturing equipment during maintenance activities and abrasive operations, such as wafer grinding and splitting operations. The deliverable will be further used in the workpackage dedicating to identifying risk management tools for the semiconductor industry.