An Efficient Design of FSM Based 32-Bit Unsigned Pipelined Multiplier Using Verilog HDL

This paper shows a modification to FSM based 32-bit pipelined multiplier. It uses carry look ahead adders (CLA’s) and Carry Select Adders (CSA) in place of ripple carry adders (RCA’s) in 32-bit FSM based pipelined multiplier for reducing the carry propagation delay. The proposed hardware design is based on shift and add algorithm for multiplication process.

Related Organizations

PSG College of Technology
India
PSG College of Technology
India

Keywords

Carry look ahead adders (CLA); Ripple carry adders (RCA); Carry select adder (CSA); Finite state machine (FSM); Partial product generators

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