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Analysis of Ternary logic arithmetic circuits

Authors: Y. Mallikarjuna Rao;

Analysis of Ternary logic arithmetic circuits

Abstract

{"references": ["1.\tSulochana, V., Venkataiah, C., Agrawal, S., & Singh, B. (2023). Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic. IETE Journal of Research, 69(3), 1328-1340.", "2.\tVenkataiah, C., Satya-Prakash, V. N. V., Mallikarjuna, K., & Prasad, T. J. (2019). Investigating the effect of chirality, oxide thickness, temperature and channel length variation on a threshold voltage of MOSFET, GNRFET, and CNTFET. J Mech Continua Math Sci. https://doi. org/10.26782/jmcms. spl, 3(2019.09), 00018.", "3.\tKumbhare, V. R., Paltani, P. P., Venkataiah, C., & Majumder, M. K. (2019). Analytical study of bundled MWCNT and edged MLGNR interconnects: impact on propagation delay and area. IEEE Transactions on Nanotechnology, 18, 606-610.", "4.\tVenkataiah, C., Satyaprasad, K., & Jayachandra Prasad, T. (2019). Insertion of an Optimal Number of Repeaters in Pipelined Nano-interconnects for Transient Delay Minimization. Circuits, Systems, and Signal Processing, 38, 682-698.", "5.\tVenkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). FDTD algorithm to achieve absolute stability in performance analysis of SWCNT interconnects. Journal of computational electronics, 17, 540-550.", "6.\tVenkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). Crosstalk Induced Performance Analysis of Single Wall Carbon Nanotube Interconnects Using Stable Finite-Difference Time-Domain Model. Journal of nanoelectronics and optoelectronics, 13(6), 846-855.", "7.\tVenkataiah, C., Satyaprasad, K., & Prasad, T. J. (2018). Signal integrity analysis for coupled SWCNT interconnects using stable recursive algorithm. Microelectronics journal, 74, 13-23.", "8.\tSaikumarReddy, C. V., Venkataiah, C., Kumar, V. R., Maheshwaram, S., Jain, N., Dasgupta, S., & Manhas, S. K. (2018). Design and simulation of CNT based nano-transistor for greenhouse gas detection. Journal of Nanoelectronics and Optoelectronics, 13(4), 593-601.", "9.\tVenkataiah, C., Prasad, K. S., & Prasad, T. J. C. (2016, October). Effect of interconnect parasitic variations on circuit performance parameters. In 2016 International Conference on Communication and Electronics Systems (ICCES) (pp. 1-4). IEEE.", "10.\tVenkataiah, C., Ramanjaneyulu, N., Rao, Y. M., Prakash, V. S., Murthy, M. L., & Rao, N. S. (2022). Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies. Nanotechnology for Environmental Engineering, 7(3), 775-781."]}

Complementary metal oxide semiconductor (CMOS) technology has facing a problems when down scaling a device. However, CMOS have the limitations in lower technology, to avoid the drawbacks of CMOS researchers have introduced the carbon nan-tube FETS (CNTFETs). CNTFETs have the flexibility to change the threshold voltage of the device by changing the device dimensions such as length and width. Hence this property of the CNTFET is useful for designing of multi-valued logic (MVL) such as ternary logic. These types of MVL logical circuits are useful for reduction in the hardware of the circuit. Hence, it can be reduce the wiring connection complexity compared to that of other digital logic circuits. This paper presents a CNTFET based ternary arithmetic circuits for the improvement of device complexity because all arithmetic digital circuits are play a major role in many electronic applications. We have verified the functionality of ternary half adder by using CNTFET. All the simulations have done in HSpice using 32nm technology node.

Keywords

MVL logic circuits, ternary arithmetic logic circuits, Carbon Nanotube based FETs

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