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This is the public repo for the research artifact used in the submission of ISFPGA'23: Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking. In particular: The file "fpga23-artifact-dhls-dhls-30-nov-spr-1-dec.zip" contains our contribution, and experiment results in raw log files; The file "fpga23-artifact-shls.zip" contains the results produced from Vivado HLS, which are used for creating figure 10.
| selected citations These citations are derived from selected sources. This is an alternative to the "Influence" indicator, which also reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically). | 1 | |
| popularity This indicator reflects the "current" impact/attention (the "hype") of an article in the research community at large, based on the underlying citation network. | Average | |
| influence This indicator reflects the overall/total impact of an article in the research community at large, based on the underlying citation network (diachronically). | Average | |
| impulse This indicator reflects the initial momentum of an article directly after its publication, based on the underlying citation network. | Average |
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