Image processing in machine vision is a challenging task because often real-time requirements have to be met in these systems. To accelerate the processing tasks in machine vision and to reduce data transfer latencies, new architectures for embedded systems in intelligent cameras are required. Furthermore, innovative processing approaches are necessary to realize these architectures efficiently. Marching Pixels are such a processing scheme, based on Organic Computing principles, and can be applied for example to determine object centroids in binary or gray-scale images. In this paper, we present a processing pipeline for smart camera systems utilizing such Marching Pixel algorithms. It consists of a buffering template for image pre-processing tasks in a FPGA to enhance captured images and an ASIC for the efficient realization of Marching Pixel approaches. The ASIC achieves a speedup of eight for the realization of Marching Pixel algorithms, compared to a common medium performance DSP platform.