Cache memory, often referred to as cache, is a supplementary memory gadget that saves regularly used instructions and records so as for the control processing unit (CPU) of a laptop to perform them extra speedy. A pc's primary memory is supplemented through the cache, which acts as an extension of it. Internal random-get right of entry to reminiscences (RAMs) that utilize semiconductor-based transistor circuits are used in both fundamental reminiscence and cache. The cache stores handiest a replica of the most often used information or programme codes from the main memory. The cache's decreased length minimizes the time it takes to perceive information and send it to the CPU for processing. The topic of reconfigurable cache reminiscence is discussed in this have a look at. In this paper VHDL (Very high stage hardware Description Language) is used to design and put in force a two Dimensional Reconfigurable Cache reminiscence (cache length and associativity) the use of FPGA (discipline-Programmable Gate Array). In this design the cache memory architecture permits to exchange the reminiscence employer and length of its reminiscence through using a cache size controller unit and way controller unit, to enhance the processor performance and decrease the power intake, and the use of all to be had reminiscence length for all viable organizations that may be selected. The consequences show the simulation of the design. This layout is synthesized the use of (Xilinx ISE layout Suite 13.four) and simulated the use of (Xilinx ISim simulator).Verilog hardware Description Language is used to layout cache memory which involves direct mapping and set associative cache. In addition set associative cache entails two-manner, 4-manner and eight-way. On this layout of cache memory structure, the mapping technique may be numerous the use of a controller unit. To boom getting access to velocity and optimize power through disable unused cache reminiscence set blocks