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Cache side-channel attacks allow adversaries to learn sensitive information about co-running processes by using only access latency measures and cache contention.This vulnerability has been shown to lead to several microarchitectural attacks. As a promising solution, recent work proposes Randomization-based Protected Caches (RPCs). RPCs randomize cache addresses, changing keys periodically so as to avoid long-term leakage. Unfortunately, recent attacks have called the security of state-of-the-art RPCs into question.In this work, we tackle the problem of formally defining and analyzing the security properties of RPCs. We first give security definitions against access-based cache sidechannel attacks that capture security against known attacks such as Prime+Probe and Evict+Probe. Then, using these definitions, we obtain results that allow to guarantee security by adequately choosing the rekeying period, the key generation algorithm and the cache randomizer, thus providing security proofs for RPCs under certain assumptions.
Computer engineering. Computer hardware, Cache side-channel attacks, Randomization-based protected caches, Security definition, Randomly-mapped caches, Information technology, T58.5-58.64, Cache memory -- Security measures, Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica, 004, 620, TK7885-7895, :Informàtica::Seguretat informàtica [Àrees temàtiques de la UPC], Timing attacks, Pseudo-random functions, Memòria cau -- Mesures de seguretat
Computer engineering. Computer hardware, Cache side-channel attacks, Randomization-based protected caches, Security definition, Randomly-mapped caches, Information technology, T58.5-58.64, Cache memory -- Security measures, Àrees temàtiques de la UPC::Informàtica::Seguretat informàtica, 004, 620, TK7885-7895, :Informàtica::Seguretat informàtica [Àrees temàtiques de la UPC], Timing attacks, Pseudo-random functions, Memòria cau -- Mesures de seguretat
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