This data set contains the results presented in the paper "Custom Multi-Cache Architectures for Heap-Manipulating Programs", published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) in 2016. The data set consists of two parts, a Microsoft Excel file ('FPGA_implementation_results.xlsx') and a Matlab script ('plot_cache_performance.m', in combination with measurement results in an ascii file). The Excel file contains - the FPGA resource utilisation, - execution time measurements, - hit rate measurement of the multi-cache system, - and power measurements of different FPGA designs with different on-chip cache configurations. The resource utilisation is split into FPGA slices, LUTs, FlipFlops, DSP slices and block RAMs. Results in this file can be found in Table I-IV in the paper. Please refer to the paper for more information or email f.winterstein12@imperial.ac.uk. The Matlab script loads a data file ('cache_performance_N16384_L1') containing the hit rate measurements for different cache sizes of two direct-mapped cache with 64bit line width. The script produces a 3D 'skyscraper' plot, i.e. a grid of coloured bars. Each bar corresponds to the hit rate measured at the particular cache size configuration. The plot is saved in the file 'surf.pdf'. The script was used to produce Figure 4 of the paper. Please refer to the paper for more information or email f.winterstein12@imperial.ac.uk. In addition to this description, we include an author copy of the paper. Note that this is not the official version of the paper. Please cite the original IEEE TCAD article if you use the data.