The design and construction of the SpiNNaker machine was supported by EPSRC (the UK Engineering and Physical Sciences Research Council) under grants EP/D07908X/1 and EP/G015740/1, in collaboration with the universities of Southampton, Cambridge and Sheffield and with industry partners ARM Ltd, Silistix Ltd and Thales, and by the European Research Council under the BrainScales project (EU-FP7-FET-269921). Ongoing development is supported by the EU ICT Flagship Human Brain Project (FP7-604102), in collaboration with many university and industry partners across the EU and beyond, and our own exploration of the capabilities of the machine is supported by the European Research Council under the European Union's Seventh Framework Programme (FP7/2007-2013) / ERC grant agreement 320689. SpiNNaker has been 15 years in conception and 10 years in construction, and many folk in Manchester and in our various collaborating groups around the world have contributed to get the project to its current state. We gratefully acknowledge all of these contributions. spI/O is available from GitHub: https://github.com/SpiNNakerManchester/spio The version provided here corresponds to GitHub tag spin5_fpga_00210416, available from: https://github.com/SpiNNakerManchester/spio/tree/spin5_fpga_00210416

SpiNNaker is a massively-parallel machine designed for very-large scale neural net simulation in real time. SpiNNaker systems are based on multi-core SpiNNaker chips, which contain 18 energy-efficient ARM cores and a bespoke communications infrastructure optimized for the transmission of simulated neuronal spikes. SpiNNaker systems are built using SpiNN-5 boards, populated with 48 SpiNNaker chips interconnected in a hexagonal 2D mesh. Boards are connected together using high-speed serial links provided by 3 on-board Xilinx Spartan6 FPGAs. The spI/O library contains a series of FPGA designs and reusable modules for I/O and internal connectivity in SpiNNaker systems. The designs directory contains ready-to-synthesise FPGA designs based on the modules in the library. One of the example designs is spiNNlink, the FPGA-based SpiNNaker SpiNN-5 board-to-board high-speed serial link interconnect. See designs/README.md for general advice on how to build these designs. The modules directory contains a selection of reusable Verilog modules, all of which share the common interface described in README.md. See the specific README.md file included with each module for general information or see the module itself for a concrete interface description.

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