High-level synthesis (HLS) tools automatically transform a high-level program, for example in C/C++ into a low-level hardware description. A key challenge in HLS tools is scheduling, i.e. determining the start time of all the operations in the untimed program. There are three approaches to scheduling: static, dynamic and hybrid. A major shortcoming of existing approaches to scheduling is that the tools either assume the worst-case timing behaviour, which can cause significant performance loss or area overhead, or use simulation-based approaches, where can cause significant time to explore a large number of program traces. To rectify this, we propose a probabilistic model to efficiently explore timing behaviour of HLS hardware from all these scheduling approaches. We show how to model the hardware behaviour into Petri nets for performance analysis. Our framework offers insights to assist hardware engineers and HLS tools in setting their expectations of the hardware performance from the input code and performing optimal hardware optimisation. As a particular application, we show how to automatically infer the optimal initiation interval~(II) for statically-scheduled components forming part of a dynamically-scheduled circuit. An empirical evaluation on a range of benchmarks suggests that by using this approach, on average we achieve 9x speedup for estimating an optimal II with 2% overhead in area-delay product (ADP) compared to the design with an II by exhaustive search, while the static analysis in Vitis HLS causes 112% ADP overhead and the throughput analysis in Dynamatic causes 17% ADP overhead.