Multiplication and division are the most critical arithmetic operation carried out in any digital logic algorithm such as digital signal processing, in cryptography for encryption and decryption algorithm, ALU design and in other logic computation. Thrust in higher processing speed and low power has not only tendered the need for improvements in processor technologies but also in exploring new algorithms. Vedic Mathematics’ potential can be unleashed in an effective way to design and implement the algorithm for multiplication and division. Through this paper Vedic mathematics application in VLSI design is reviewed and it is found that Vedic sutras based algorithms in digital logic design has resulted in simpler architecture, better speed and higher power efficiency