{"references": ["1.\tWikipedia, Logic gate, Available at: https://en.wikipedia.org/wiki/Logic_gate, [Accessed on: 4/2020].", "2.\tM. Morris Mano, Michael D. Ciletti, 2012, Digital Design Digital: With an Introduction to the Verilog HDL, 5th edition, Prentice Hall, pp. 576, Available at: https://nitsri.ac.in/Department/Computer%20Science%20&%20Engineering/digital_design-__morris_mano-fifth_edition.pdf.", "3.\tTutorialspoint.com, Computer Logical Organization Tutorial, Available at: https://www.tutorialspoint.com/computer_logical_organization/logic_gates.htm.", "4.\tElectronics hub, (2019), Introduction to logic gates, Available at: electronicshub.org/introduction-to-logic-gates/."]}

Right now, we have built up a circuit that gives the yield for 4-Logic gates of "AND, NAND, OR, NOR" at the same time by taking just two information sources "A" and "B". Already we have each circuit for every Logic gate however now in our new circuit; we created four Logic entryways in a solitary circuit. Hence we can diminish the size of the extraordinary circuits. Rather than utilizing four IC's for four Logic gates on the off chance that we utilize this single IC for all the four Logic entryways, at that point the space utilized for the staying three IC's can be utilized for different purposes. This circuit is extremely simple to plan.